The present invention relates to a semiconductor device and a method of fabricating the same.
Recently, so-called double-gate-structure MOSFETs are developed, and a MOSFET having a Fin-shaped semiconductor layer is called a FinFET. This FinFET is considered to be promising as a next-generation transistor structure because the fabrication cost is low and the cutoff characteristics are good.
A planar MOSFET, however, is superior to the FinFET in realizing a device having a high gate threshold voltage or in fabricating an analog device. In an actual LSI, therefore, both the planar MOSFET and FinFET must be embedded, and a simple fabrication process of embedding both the planar MOSFET and FinFET is being sought.
Unfortunately, when both the planar MOSFET and FinFET are to be embedded, the surface of a gate electrode material is roughened when it is deposited, and this makes the formation of a fine gate pattern impossible.
A reference concerning a method of fabricating a semiconductor device in which both the planar MOSFET and FinFET are embedded is as follows.
Japanese Patent Laid-Open No. 2005-19996